1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having wafer-level circuits and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward multi-function and high electrical performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM), and 3D IC chip stacking technologies.
FIG. 1A is a schematic cross-sectional view of a conventional semiconductor package 1. Referring to FIG. 1A, the semiconductor package 1 has a packaging substrate 14 having a plurality of bonding pads 140 having a large pitch, a through silicon interposer (TSI) 10 disposed on the packaging substrate 14, and a semiconductor chip 12 disposed on the through silicon interposer 10 and having a plurality of electrode pads 120 having a small pitch. The through silicon interposer 10 has a plurality of through silicon vias (TSVs) 100 formed therein and a redistribution layer (RDL) structure 101 formed on the TSVs 100. The RDL structure 101 is electrically connected to the bonding pads 140 of the packaging substrate 14 through a plurality of conductive elements 18. An underfill 13 is formed between the through silicon interposer 10 and the packaging substrate 14 for encapsulating the conductive elements 18. The electrode pads 120 of the semiconductor chip 120 are electrically connected to the TSVs 100 of the through silicon interposer 10 through a plurality of solder bumps 121. Further, an underfill 13 is formed between the through silicon interposer 10 and the semiconductor chip 120 for encapsulating the solder bumps 121.
If the semiconductor chip 12 is directly disposed on the packaging substrate 14, joints formed between the solder bumps 121 of the semiconductor chip 12 and the bonding pads 140 of the packaging substrate 14 can be adversely affected by a big CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chip 12 and the packaging substrate 14, thus easily resulting in delamination of the solder bumps 121 from the packaging substrate 14. Further, the CTE mismatch between the semiconductor chip 12 and the packaging substrate 14 induces more thermal stresses and leads to more serious warpages, thereby reducing the reliability of electrical connection between the semiconductor chip 12 and the packaging substrate 14 and even resulting in failure of a reliability test.
Therefore, the through silicon interposer 10 made of a semiconductor material close to the semiconductor chip 12 is provided so as to effectively overcome the above-described drawbacks.
However, to form the TSVs 100 of the through silicon interposer 10, a plurality of through holes need to be formed in the through silicon interposer 10 and filled with a metal material, which incurs a high cost. For example, for a 12-inch wafer, the TSV cost occupies about 40% to 50% of the total cost for fabricating the through silicon interposer 10. Consequently, the cost of the final product is increased.
Further, the fabrication of the through silicon interposer 10 is quite complicated, thus resulting in a low yield of the semiconductor package 1.
To overcome the above-described drawbacks, a semiconductor package 1′ without a through silicon interposer, as shown in FIG. 1B, is proposed. Referring to FIG. 1B, a plurality of semiconductor chips 12 are disposed on a circuit portion 11 on a carrier (not shown) through a plurality of solder bumps 121. Then, an encapsulant 16 is formed on the circuit portion 11 for encapsulating the semiconductor chips 12 so as to protect the semiconductor chips 12 and increase the rigidity of the semiconductor package 1′. Thereafter, the carrier (not shown) on the lower side of the circuit portion 11 is removed and an insulating layer 17 is formed on the lower side of the circuit portion 11. The circuit portion 11 is partially exposed from the insulating layer 17 so as for a plurality of conductive elements 18 such as solder balls to be formed thereon.
However, since the gap between the semiconductor chips 12 is very small, when the carrier on the lower side of the circuit portion 11 is removed, stresses induced by a CTE mismatch between the semiconductor chips 12, inter-metal dielectric (IMD) layers of the circuit portion 11 and the encapsulant 16 can easily cause cracking of the IMD layers of the circuit portion 11 and even cause cracking of the solder bumps 121, for example, a crack k of FIG. 1B.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.